The present invention relates to a semiconductor component having a substrate of a first conductivity type with a surface at which a plurality of separate wells of a second conductivity type with a more highly doped edge layer of the second conductivity type are disposed and isolated from one another by pn junctions. The invention also relates to a method for fabricating a semiconductor component.
In integrated power switches produced in a plurality of wells in the surface of a semiconductor, operating states frequently occur in which a potential of a drain electrode of a DMOS transistor becomes negative relative to a substrate potential. In that case, minority carriers (electrons) are injected into the pxe2x88x92-doped substrate from at least one of the wells. Due to the very high carrier lifetime in the substrate, the range of those minority carriers is very high (a few mm). Each further n-type well situated in the crystal acts as a collector or as a drain for those minority carriers. The functioning of the components (pMOS, nMOS, PNPs, NPNs, etc.) situated in the further n-type wells is impaired by those parasitic currents, which can lead to a functional failure of the circuit. The injecting well (emitter), the substrate (base) and each further well (collector) thus form an NPN transistor. The current flowing through that NPN transistor is called xe2x80x9cparallel-path currentxe2x80x9d or xe2x80x9ccross currentxe2x80x9d.
German Published, Non-Prosecuted Patent Application DE 44 11 869 A1, corresponding to U.S. Pat. No. 5,719,431, describes a structure in which the parallel-path current is suppressed through the use of two measures. The first measure resides in placing extraction rings around the injecting component, or the component forming the emitter, and connecting them to the source connection of the DMOS transistor. The second measure resides in using a p+-pxe2x88x92-type substrate. The extraction rings act as a collector, so that the further wells are practically no longer able to take up a parallel-path current. As a result of the doping gradient between the p+-type region and the pxe2x88x92-type region in the substrate, a drift field is built up which prevents the injection of the minority carriers into the substrate.
Although that structure has proved to be effective for suppressing parallel-path currents, it does have two not inconsiderable disadvantages. Firstly, the required p+-type or p+-pxe2x88x92-type substrate is more expensive than the pxe2x88x92-type substrate that is used as a standard substrate. Secondly, an existing circuit layout cannot be made parallel-path current proof without far-reaching corrections to the layout: it is necessary to provide the extraction rings. Finally, the extraction rings mean that a larger chip area is required, all the more so since it is necessary to dissipate comparatively large currents which may become greater than the rated current of the component and may be as much as 10 A.
It is accordingly an object of the invention to provide a semiconductor component with a structure for avoiding parallel-path currents, in which individual wells in the component are not influenced by minority carriers injected into a substrate, as well as a method for fabricating a semiconductor component, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component, comprising a substrate having a first conductivity type and a surface; a plurality of separate wells of a second conductivity type with a more highly doped edge layer of the second conductivity type disposed at the surface of the substrate and isolated from one other by pn junctions; and an insulating well of the first conductivity type completely surrounding at least one of the separate wells and having a higher doping than the substrate.
The invention prevents minority carriers situated in the substrate from penetrating into the wells in large numbers, or prevents minority carriers from reaching the substrate at all from the wells and, consequently, parallel-path currents from being able to arise.
In this case, the wells surrounded by an insulating well may be inner wells that inject minority carriers or wells that take up minority carriers. By virtue of the fact that the doping of the insulating well is higher than that of the substrate, an opposing field builds up between the substrate and the substrate supplementary layer and prevents the minority carriers from penetrating further into the insulating well.
In accordance with another feature of the invention, the insulating well includes a substrate supplementary layer. on the substrate and a side wall between the substrate supplementary layer and the surface of the semiconductor.
In both embodiments, the well is xe2x80x9chermeticallyxe2x80x9d shielded by the insulating well with the substrate supplementary layer and the side wall of the respective first conductivity type in the semiconductor against the rest of the semiconductor. In other words, in particular, it is shielded against the remaining wells in the semiconductor, with the result that parallel-path currents can no longer issue from the shielded well or can no longer reach the latter.
In accordance with a further feature of the invention, there is provided a spacer layer of the first conductivity type between the substrate supplementary layer and the edge layer. The spacer layer is more weakly doped than the substrate supplementary layer or the side wall, thereby ensuring the dielectric strength of the component. In this case, the spacer layer may include two or more partial layers, with the result that the dielectric strength can be set depending on the number of partial layers.
With the objects of the invention in view there is also provided a method for fabricating a semiconductor component, which comprises providing a substrate having a first conductivity type and a surface of the component on the substrate; producing a plurality of separate wells at the surface of the substrate, the separate wells having a second conductivity type and a more highly doped edge layer of the second conductivity type; producing connection and control electrodes in the separate wells for fabricating component structures; and producing an insulating well around at least one of the separate wells, the insulating well having the first conductivity type and a doping higher than the substrate.
In accordance with another mode of the invention, in order to produce the insulating well, a substrate supplementary layer is produced on the substrate and a vertical side wall contiguous with the substrate supplementary layer is produced between the wells.
In accordance with a concomitant mode of the invention, a spacer layer of the first conductivity type is produced between the insulating well and the edge layer and is more weakly doped than the insulating well.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor component with a structure for avoiding parallel-path currents and a method for fabricating a semiconductor component, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.